logicBC is a company that provides ASIC/FPGA design and verification services in the Aerospace and Automotive industries. At the moment we are looking for engineers to work with us on ASIC verification project for our client.

As Junior/Graduate ASIC verification engineer you will:

work on projects for the largest players in ASIC world,

verify digital circuits using SystemVerilog language and the most modern ASIC verification methodology - UVM,

create project documentation for designs certifications,

work on a structured and well planned projects (we use Requirements Driven Development Processes in our projects).

Our requirements:

recent graduate of a Master degree or student in final year of university studies in computer science, electronics or related fields,

very good knowledge of English that allows everyday communication and documentation creation,

good understanding of Digital Design principles (on academic level),

good understanding of SoC (on academic level),

knowledge of at least one hardware description language (VHDL or Verilog/SystemVerilog),

good knowledge of Object Oriented Programming,

ability and willingness to learn and work as part of a team,

a valid work permit for Poland/European Union.

Nice to have:

knowledge of communication interfaces such as I2C, SPI,

understanding of configuration management and change management principles,

basics knowledge of scripting languages,

experience of previous projects (also academic ones) with FPGA usage,

experience of using modern simulation tools (Modelsim/Questa, Simvision).

What we offer:

very competitive salary package adequate to competencies,

full employment contract,

working on challenging projects,

support of senior engineers to allow you quickly gain technical experience.